Simple Analysis of Pipeline Performance and Cycle Optimization in Computer Architecture

  • Shaoshao Xu Xiamen University
Ariticle ID: 2497
131 Views, 67 PDF Downloads
Keywords: Pipeline, Throughput Rate, Speed up Ratio, Efficiency, Loop Unrolling, Instruction Scheduling

Abstract

This paper first summarizes the performance analysis of pipeline and some problems related to the performance of pipeline, and then introduces the how to loop optimization in detail. Pipelining technology is a very important technology in the field of computer. Using pipelining technology, multiple executing device in the computer work in parallel. The idea of parallelism comes from the traditional production assembly-line model of factory. As early as in the 1960s, some high-end machines have begun to use pipeline technology. Up to now, the pipeline technology has been very mature. The IBM7030 was the first computer to adopt pipeline technology. Pipelined processor can meet the higher requirements of computer operation and improve the performance of CPU. Pipelined processor has become an important and indispensable part of computer architecture.

References

Chopra, R. (2008). Advanced Computer Architecture. S. Chand Publishing.

Advanced Computer Architecture Rajiv Chopra Chand Publishing, 2008.

H. Tuncer, I., Gülcat, Ü., R. Emerson, D., & Matsuno, K. (2007a). Parallel Computational Fluid Dynamics 2007. Springer.

Understanding Bottlenecks. (2020, November 13). Investopedia.

Cosnard, M., Ferreira, A., & Peters, J. (1994). Parallel and Distributed Computing: Theory and Practice. (First Canada-France Conference, Montreal, Canada, May 19–21, 1994. Proceedings ed.). Springer Science & Business Media.

Speedup Ratio and Parallel Efficiency: TechWeb: Boston University. (n.d.).

A. Fisher, J., Faraboschi, P., & Young, C. (1981). Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools. Denise E.M Penrose.

Matthes, E. (2020). CUDA C Programming Authoritative Guide.

Published
2021-01-03
How to Cite
Xu, S. (2021). Simple Analysis of Pipeline Performance and Cycle Optimization in Computer Architecture. Journal of Networking and Telecommunications, 3(1), 8-13. https://doi.org/10.18282/jnt.v3i1.2497
Section
Original Research Articles