Call for Papers for the Special Issue: Journal of Networking and Telecommunications

The Introduction of the Special Issue

In recent years, through the wide expansion of multiprocessor system-on-chips (MPoCs) and multi/many-core architecture, hundreds of processing cores on a single chip are simultaneously working toghether. Network-on-Chip (NoC) approach has been considered as an efficient communication paradigm which can be appropriately replaced by the traditional bus interconnect. Some interesting features of NoC such as scalable infrastructure and modularity, high communication bandwidth, improved power dissipation and network latency convince the system designers to widely exploit NoC structure instead of bus-based or point-to-point on-chip communication platforms.

The electrical NoC was the first proposed NoC platform which has been used in recent commercial multi/many-core processor. Through technology scaling, there are some drawbacks for ENoC such as limited bandwidth, latency and power consumption scaling which motivate researchers to work on new trends in NoC. Silicon photonic (Optical Network-on-Chip), on-chip wireless communication and also 3D-stacking of communication layer are some of new proposed approaches. Various challenges and issues of these types of NoC can be targeted for this Special issue.

The Research Scope of the Special Issue

·Electrical Network-on-Chip (ENoC) and its challenges

·Optical Network-on-Chip (ONoC) and its challenges

·Wireless Network-on-Chip (WNoC) and its challenges

·3D stacking design of Network-on-Chip and its challenges

·Reliability analysis of various types of Network-on-Chip

·Application mapping and scheduling onto Network-on-Chip

·Performance, power consumption and thermal issues of Network-on-Chip

Submission guidelines

All papers should be submitted via the Journal of Networking and Telecommunications submission system: http://ojs.piscomed.com/index.php/JNT

Submitted articles should not be published or under review elsewhere. All submissions will be subject to the journal’s standard peer review process. Criteria for acceptance include originality, contribution, scientific merit and relevance to the field of interest of the Special Issue.

Important Dates

Paper Submission Due: July 31 , 2019

The Lead Guest Editor

Meisam Abdollahi

He is a Ph.D. student who joined Dependable System Design Laboratory in the School of Electrical and Computer engineering, at the University of Tehran, Iran. in Fall 2012. He has got his BSc degree in hardware computer engineering from Iran University of Science and Technology and Msc from Sharif University of Technology.

Guest Editors

Dr. Farzad Razi, University of Tehran

Dr. Taghil Adl, University of Tehran

Dr. Alireza Namazi

Department of Computer Engineering, University of Tehran, North Kargar St., Tehran, Iran.

Dr. Mohammad Baharloo

Network LAB, Engineering Campus of University of Tehran,Electrical and Computer Engineering Department,Amir Abad Avenue, Tehran, Iran.

Dr. Mohammad Mirzaei

Dependable System Design (DSD) LAB,Engineering Campus of University of Tehran,Electrical and Computer Engineering Department,Amir Abad Avenue, Tehran, Iran.